University of Texas at Austin
Keshav Pingali




phone (512) 232-6567

office POB 4.126

Keshav Pingali

Core Faculty GSC Faculty

W. A. "Tex" Moncrief, Jr. Chair in Distributed and Grid Computing

Director Center for Distributed and Grid Computing

Professor Computer Science

Centers and Groups

Research Interests

Programming languages High-Performance Computing


Keshav Pingali received the B.Tech. degree from I.I.T. Kanpur (1978), the S.M. and E.E. degrees from M.I.T (1983), and the from M.I.T.(1986) in Computer Science.

Between 1986 and 2006, he was on the faculty in the CS and ECE Departments at Cornell University, where he held the Indian Chair of Computing. Since 2006, he has been a professor in the CS department at the University of Texas at Austin, where he holds the W.A."Tex" Moncrief Chair of Computing. 

Pingali is a Fellow of the ACM, IEEE, and AAAS. He was co-Editor-in-chief of ACM TOPLAS, and serves on the editorial boards of the International Journal of Parallel Programming, and Distributed Computing. He was on the Gordon Bell Prize Committee (2013-2017) and he has served on the NSF CISE Advisory Committee (2009-2012). 

Pingali works on parallel and distributed computing for big-data and computational science workloads. In particular, his group is interested in developing programming models, languages, compilers and runtime systems that enable application programmers to write programs at a high level of abstraction without compromising on execution efficiency. 

His group’s most recent work is focused on efficient parallel execution of "irregular applications," which process large amounts of unstructured data. The group has designed a new programming model called the "operator formulation" for writing these applications at a high level of abstraction, and have implemented this model in the Galois compiler and runtime system. This system has been used in several DARPA projects for implementing finite-element mesh generation, refinement and partitioning, for real-time intrusion detection in computer networks, for implementing parallel tools for chip design including timing analysis, placement and routing, and for high-performance graph analytics. 

Earlier research focused on compiler techniques for automatic management of memory-hierarchies. Some of these have been patented and are in use in industry compilers. 

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